Today s class. Digital Logic. Informationsteknologi. Friday, October 19, 2007 Computer Architecture I - Class 8 1
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- Augusta de Meyer
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1 Today s class Digital Logic Friday, October 19, 2007 Computer Architecture I - Class 8 1
2 Digital circuits Two logical values Binary 0 (signal between 0 and 1 volt) Binary 1 (signal between 2 and 5 volts) Gates are small electronic devices that compute various functions of these twovalued signals Friday, October 19, 2007 Computer Architecture I - Class 8 2
3 Transistor Inverter (NOT Gate) When the input voltage, V in, is below a critical value the transistor turns off and acts like an infinite resistance, so V out is very close to V cc, an externally regulated voltage (typically 5 V) When V in exceeds the critical value the transistor switches on and acts like a wire, causing V out to be pulled down to ground (0 V) Friday, October 19, 2007 Computer Architecture I - Class 8 3
4 NAND Gate If both V 1 and V 2 are high, both transistors will conduct and V out will be low If either V 1 or V 2 is low the corresponding transistor will turn off and the V out will be high Friday, October 19, 2007 Computer Architecture I - Class 8 4
5 NOR Gate If either V 1 or V 2 is high the corresponding transistor will turn on and V out will be pulled to ground (0 V) If both V 1 and V 2 are low then V out will remain high Friday, October 19, 2007 Computer Architecture I - Class 8 5
6 Gates and Boolean Algebra Friday, October 19, 2007 Computer Architecture I - Class 8 6
7 The Majority Function Friday, October 19, 2007 Computer Architecture I - Class 8 7
8 Boolean Circuits Write down the truth table for the function Provide inverters to generate the complement (NOT) of each input Draw an AND gate for each term with a 1 in the result column Wire the AND gates to the appropriate inputs Feed the output of all the AND gates into an OR gate Friday, October 19, 2007 Computer Architecture I - Class 8 8
9 Boolean Function Notation Truth table can get too large for more than 3 or 4 inputs Use a notation that specifies which combinations of inputs produce an output of 1 M = ABC + ABC + ABC + ABC Friday, October 19, 2007 Computer Architecture I - Class 8 9
10 Using Only NAND and NOR Friday, October 19, 2007 Computer Architecture I - Class 8 10
11 Circuit Equivalence Friday, October 19, 2007 Computer Architecture I - Class 8 11
12 Boolean Algebra Identities Friday, October 19, 2007 Computer Architecture I - Class 8 12
13 Alternative Symbols for Some Gates Friday, October 19, 2007 Computer Architecture I - Class 8 13
14 Three Circuits for XOR Friday, October 19, 2007 Computer Architecture I - Class 8 14
15 In-Class Exercise Use a truth table to show that X = (X AND Y) OR (X AND NOT Y) Show how the AND function can be constructed from two NAND gates Friday, October 19, 2007 Computer Architecture I - Class 8 15
16 Integrated Circuits Friday, October 19, 2007 Computer Architecture I - Class 8 16
17 Multiplexer Friday, October 19, 2007 Computer Architecture I - Class 8 17
18 Decoder Friday, October 19, 2007 Computer Architecture I - Class 8 18
19 Comparator Friday, October 19, 2007 Computer Architecture I - Class 8 19
20 Shifter Friday, October 19, 2007 Computer Architecture I - Class 8 20
21 Half Adder (a) (b) Friday, October 19, 2007 Computer Architecture I - Class 8 21
22 Full Adder Friday, October 19, 2007 Computer Architecture I - Class 8 22
23 Arithmetic Logic Unit Friday, October 19, 2007 Computer Architecture I - Class 8 23
24 SR Latch Friday, October 19, 2007 Computer Architecture I - Class 8 24
25 Clocked SR Latch A clocked SR latch. Friday, October 19, 2007 Computer Architecture I - Class 8 25
26 Clocked D Latch A clocked D latch. Friday, October 19, 2007 Computer Architecture I - Class 8 26
27 Flip-Flops Friday, October 19, 2007 Computer Architecture I - Class 8 27
28 D Flip-Flop Friday, October 19, 2007 Computer Architecture I - Class 8 28
29 Latch and Flip-Flop Symbols Friday, October 19, 2007 Computer Architecture I - Class 8 29
30 Octal Flip-Flop (8-Bit Register) Friday, October 19, 2007 Computer Architecture I - Class 8 30
31 Memory Friday, October 19, 2007 Computer Architecture I - Class 8 31
32 Buffers (a) A noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer. Friday, October 19, 2007 Computer Architecture I - Class 8 32
33 4-Mbit Memory Chips Friday, October 19, 2007 Computer Architecture I - Class 8 33
34 CPU Chips The logical pinout of a generic CPU. Arrows indicate input signals and output signals. Short diagonal lines indicate that multiple pins are used. Friday, October 19, 2007 Computer Architecture I - Class 8 34
35 Computer Buses A bus is a common electrical pathway between multiple devices Friday, October 19, 2007 Computer Architecture I - Class 8 35
36 Masters and Slaves Active devices which can initiate bus transfers are called masters Passive devices which wait for requests are called slaves Friday, October 19, 2007 Computer Architecture I - Class 8 36
37 The Pentium 4 Friday, October 19, 2007 Computer Architecture I - Class 8 37
38 The Pentium 4 s Logical Pinout Names in upper case are the official Intel names for individual signals. Names in mixed case are groups of related signals or signal descriptions. Friday, October 19, 2007 Computer Architecture I - Class 8 38
39 Pipelining on the Pentium 4 s Memory Bus Friday, October 19, 2007 Computer Architecture I - Class 8 39
40 Pentium 4 Bus Structure Friday, October 19, 2007 Computer Architecture I - Class 8 40
41 PCI Bus Arbitration The PCI bus uses a centralized bus arbiter. Friday, October 19, 2007 Computer Architecture I - Class 8 41
42 The Universal Serial Bus PCI bus is too expensive for low speed I/O devices (e.g. keyboard, mouse) USB was designed by 7 companies as a better way to attach low speed I/O devices to a computer Friday, October 19, 2007 Computer Architecture I - Class 8 42
43 USB Goals Users must not have to set switches or jumpers Users must not have to open the case Only one kind of cable, for all devices Devices should get their power from the cable Up to 127 devices should be attachable to a single computer System should support real-time devices Devices should be installable while the computer is running No reboot should be needed after installing a new device Devices should be inexpensive to manufacture Friday, October 19, 2007 Computer Architecture I - Class 8 43
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