EE141- Spring 2004 Lecture 3 EE141. Last Lectures. Design Metrics

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1 - Spring 2004 Lecture Design Metrics 1 Last Lectures Moore s law Challenges in digital IC design in the next decade. Manufacturing process Today Design metrics 2 1

2 Administrivia If you have not signed-in on the class roster, please do so after the lecture. Problems? Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function 4 2

3 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area 5 NRE Cost is Increasing 6

4 Die Cost Single die Wafer Going up to 12 (0cm) From 7 G. Moore, ISSCC

5 Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law) Yield π Dies per wafer = No. of good chips per wafer Y = 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield ( wafer diameter/2) die area 2 π wafer diameter 2 die area 10 5

6 Defects die yield α defects per unit area die area = 1+ α α is approximately die cost = f 4 (die area) 11 Some Examples (1994) Chip 86DX Metal layers 2 Line width 0.90 Wafer cost $900 Def./ cm Area mm 2 4 Dies/ wafer 60 Yield 71% Die cost $4 486 DX $ % $12 Power PC $ % $5 HP PA $ % $7 DEC Alpha 0.70 $ % $149 Super Sparc 0.70 $ % $272 Pentium 0.80 $ % $

7 Reliability Noise in Digital Integrated Circuits i(t) v(t) V DD Inductive coupling Capacitive coupling Power and ground noise 1 DC Operation Voltage Transfer Characteristic V(y) V OH f V(y)=V(x) VOH = f(vol) VOL = f(voh) VM = f(vm) V Switching Threshold M V OL V OL V OH V(x) Nominal Voltage Levels 14 7

8 Mapping between analog and digital signals 1 V OH V out V OH Slope = -1 V IH Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V in 15 Definition of Noise Margins "1" V OH V OL NM H NM L V IH Undefined Region V IL Noise margin high Noise margin low "0" Gate Output Gate Input 16 8

9 Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources 17 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; 18 9

10 Regenerative Property out out v f(v) v finv(v) v 1 v 1 finv(v) v f(v) v 2 v 0 Regenerative in v 0 v 2 Non-Regenerative in 19 Regenerative Property v 0 v 1 v 2 v v 4 v 5 v 6 A chain of inverters 5 V (Volt) v 0 1 v 1 v 2 1 Simulated response t (nsec) 20 10

11 Fan-in and Fan-out N M Fan-out N Fan-in M 21 The Ideal Gate V out g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V in 22 11

12 (V ) V o ut An Old-time Inverter NM L V M 1.0 NM H V in (V) 2 Delay Definitions V in 50% t V out t phl t plh 90% 50% 10% t t f t r 24 12

13 Ring Oscillator v 0 v 1 v 2 v v 4 v 5 v 0 v 1 v 5 T = 2 t p N 25 A First-Order RC Network R v out v in C t p = ln (2) τ = 0.69 RC Important model matches delay of inverter 26 1

14 Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power: 1 P ave = T ) V t+ T supply t+ T p( t dt = t t T i supply () t dt 27 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p 28 14

15 A First-Order RC Network R v out vin C L E 0 1 T T Vdd = Pt ()dt = V i t dd supply ()dt = V C dv dd = C V L out L 2 dd T T Vdd 1 2 E = P t cap cap ()dt = V i t out cap ()dt = C V dv = --C V L out out 2 L dd Next Lecture A First Glance at an Inverter 0 15